1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) cell process and scheme, and in particular, to buried bit line of a dynamic random access memory (DRAM) cell process and scheme.
2. Description of the Related Art
A dynamic random access memory (DRAMs) is one type of volatile memories. The basic operation principle of the DRAM utilizes the amount electric charges stored in a capacitor to represent bit ‘1’ or bit ‘0’ in the binary system for data storage. For high density requirements, the most effective method for the device size reduction now is through reducing process technology node and using a unit design technology. Another method for the device size reduction is achieved by a more effective array structure. After developing for several generations, the storage technology is usually limited by some kind of the unit layout. Also, every improvement of the unit size reduction needs a great amount of work to reduce the critical size of the etching technology.
Thus, a novel a dynamic random access memory (DRAM) cell process and scheme are desired to overcome the aforementioned problems.